A direct-conversion receiver (DCR) architecture is a radio receiver architecture that mixes a received signal with a local oscillator signal whose frequency is equal to the carrier frequency with which the desired signal was transmitted. The resulting mixed signal is then filtered using a low pass filter to obtain the desired signal and to remove the remaining unwanted signals originally residing on different carrier frequencies.
Signal frequency drift of the local oscillator (LO) is prevented by means of a phase lock loop (PLL).
Offset Problem
One of the problems with direct conversion receiver architectures is a DC offset occurring in the mixed signal. A cause of the DC offset can be local oscillator energy that leaks back to the antenna via electromagnetic coupling and then re-enters the mixer. When this leaked signal component is effectively mixed with itself, a component of the resulting signal is a 0 Hz DC signal. The DC offset can sometimes be strong enough to disrupt the baseband amplifiers of the receiver and disrupt the signal demodulation.
DC offset in direct-conversion receivers can have static and/or dynamic components.
Static Offset
Static offset is mainly generated through the above process and from device mismatch. This is where components of the system do not exactly match the ideal values of the system and DC offsets occur in the processed signal. However, if the DC offset is static and does not change over time, it can be easily minimized by adding an offset adjustment circuit.
One method of adding an offset adjustment circuit is by means of a current source controlled using an n-bit digital-to-analog converter (DAC). Such a system is shown in FIG. 1. By sending the DAC different control codes, the amount of offset current can be adjusted. In the system shown in FIG. 1, the optimum code for the DAC is determined by an analog-to-digital converter (ADC).
The calibration of the offset signal is done under firmware control; there is no direct link between the ADC & offset DAC. A look-up-table based approach is used to determine the best control codes to send to the DAC given the input from the ADC. Since this calibration requires that all of the receive chain is switched-on and it takes such a long time to perform the calibration, it would consume a lot of power to run this in real-time. Therefore, the calibration is usually done once per chip while the temperature is kept within a predetermined range.
Dynamic Offset
Typically, the above technique is effective. However, in certain architectures, the DC offset randomly flips between two distinct values—an effect called “bimodal DC offset”. This is illustrated in FIG. 2, which shows the measured optimum DAC codes in a single fabricated integrated chip while the receive chain is turned on and off repeatedly. The flip will only occur when the receiver or PLL starts. During the operation, the offset will not change.
When a receiver architecture exhibits bimodal DC offset, the technique of using a fixed calibrated DC offset fails—the system will calibrate to one of the offsets and will be unable to cope with the other one. The net result is a collapse in receiver sensitivity. A more detailed explanation of the causes of bimodal DC offset follows.
Cause of Bimodal Dynamic Offset
FIG. 3(a) shows parts of a typical receiver and PLL. Only the I-channel is shown for simplicity.
The local oscillator signal frequency generated by the PLL is divided by 2 by Rx_div to provide signal A which is used for mixing with the received signal from the antenna. The local oscillator signal frequency is also divided by 3 using LO_3 and then by 2 using LO_div. In this example, the output signal from LO_div will therefore be the 6th sub-harmonic of the local oscillator signal frequency generated by the PLL, or the 3rd sub-harmonic of signal A. Therefore, the 3rd harmonic of the output of LO_div is the same frequency as the fundamental tone of signal A. This 3rd harmonic of the output of LO_div is called signal B. Although the frequencies of signals A and B are the same, the phase of signal B can be different to the phase of signal A. This is because the output of the high frequency dividers can have two states with respect to the input. An example of this is shown FIG. 3b. Depending on initial input conditions, the divided signal may start high or start low. Although one of two states can be selected with specific initial and input conditions, it is very difficult to select one of two states directly due to self-oscillation in high frequency dividers. Therefore, signals A and B can have arbitrary states relative to each other whenever they are turned on.
Signals A and B can be coupled to the LNA input by means of parasitic paths, and for the reason described above, this can result in a DC offset forming at the output of the mixer. In this case, the interference from signals A and B at the input to the LNA will result in a dynamic DC offset at the output of the mixer, as the DC offset is dependent on the relative phase of signals A and B.
There are four possible combinations for the interference at the LNA input, dependent on the state of signals A and B. These can be conceptually expressed as (+A+B), (+A−B), (−A+B), (−A−B). Once this interference is mixed with A by the mixer, the corresponding DC offset will be either:(+A+B)·(+A),(+A−B)·(+A),(−A+B)·(−A)=(+A−B)·(+A),(−A−B)·(−A)=(+A+B)·(+A)
Consequently, the DC offset can hold one of two values: (+A+B)·(+A) or (+A−B)·(+A). This leads to a bimodal DC offset.
What is needed is a method of compensating for bimodal DC offset in order to improve receiver sensitivity.